Typical memory architectures have several drawbacks that limit their performance. This is due to the increasing data output frequencies for dynamic random access memory (DRAM). Synchronous DRAM (SDRAM) delivers data at high speed by using, among other things, an interface synchronized to the processor's internal clock. Therefore SDRAM has an output data frequency equal to the clock frequency. Double data rate (DDR) SDRAM provides data even faster by outputting data on the rising and falling edge of the clock, thus having an output data frequency of twice the clock frequency. For both SDRAM and DDR, the clock frequency is synchronous with the core frequency. For DDR II, the I/O buffers are clocked at twice the core frequency thereby providing an even greater output data frequency.
As the output data frequency increases, the signal integrity decreases. FIG. 1 illustrates a typical memory architecture in accordance with the prior art. Memory architecture 100, shown in FIG. 1, includes chipset 105. The chipset (core logic) 105 includes a memory controller 106 that controls the data flow between the system processor (not shown) and the system memory. The system memory may be contained on one or more dual in-line memory modules (DIMMs) 110. In such architecture, the command and address (CA) signals are propagated from the memory controller 106 along CA bus 108 to each DIMM 110. CA bus 108 may have, for example, eight parallel lines to propagate CA signals to the DRAM. On the board the CA signal is divided and routed to each DIMM. On each DIMM, the CA signals are successively divided to route to each DRAM over traces 109 as shown in FIG. 1. This successive division results in proportionately reduced CA signal components reaching each DRAM. Because the lengths of traces 109 are basically matched, the electrical delay to any DRAM is approximately the same. Therefore each reduced CA signal component hits the load of the respective DRAM at the same time substantially degrading each CA signal component. Additionally, the electrical reflection resulting from the trace pattern may result in interference. The extent of this interference depending upon the signal strength, and the ratio between the actual signal and the reflection.
The prior art architecture illustrated in FIG. 1 is acceptable at lower frequencies (e.g., 200 Mhz). However, as frequencies increase and the signal length becomes proportional to the physical length of the traces, the signal degradation becomes unacceptable.
The signal degradation described above has been addressed in several ways including changing the circuitry (e.g., additional resistors, duplicated lines (extra pins), etc.) and buffering the DIMM (adding extra logic chips to reduce the loading on the CA busses). These methods are costly as they amount to significant departures to industry standards for particular designs.
Another prior art memory architecture, direct Rambus™ DRAM (DRDRAM), increases data output frequency through use of a 16-bit bus (rather than the DRAM's 8-bit bus), and data pipelining. DRDRAM addresses the lumped load problem through a sequential routing scheme, but because the signal is routed through 32 DRAM chips, the signal strength eventually degrades. Additionally, the direct DRDRAM routing is across one DIMM to a connector on the motherboard and across the next DIMM, finally terminating on the motherboard, which requires additional pins at the connector. Moreover, routing through additional connectors causes signal degradation due to electrical reflection from the connectors as described above.